In data communication systems, data can be sent from a transmitter with or without an assisting clock. In the receiver, a conventional Clock Data Recovery (CDR) makes use of a Delay-Locked Loop (DLL) or a Phase-Locked Loop (PLL) to recover data and clock from the input data. Depending on its loop dynamics, a convectional Clock Data Recovery (CDR) can transfer more or less input jitter to output.
A conventional CDR may have a delay saturation problem. Delay saturation occurs when extremes of the delay chain in the Delay-Locked Loop (DLL), or in the Phase-Locked Loop (PLL), has been reached. When the delay of a controlled delay path reaches the maximum, delay saturation occurs. A conventional CDR system, such as a delay locked loop based system, usually utilizes a clock phase interpolator and/or phase selection schemes to avoid saturation or limit the range of delay control by moving the clock or choosing a clock phase. See, for example, S. Sidiropoulos and M. Horowitz, “A semidigital dual delay-locked loop,” IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, November 1997.
In some applications, however, the phase of the master clock (also known as a local clock) is preferred to be fixed. In such applications, the local master clock cannot be moved. If a conventional scheme of selecting or interpolating the clock to re-time the data were used, an extra stage might be needed to re-time the recovered data using the local master clock. The data can be retimed to generate output with reduced jitter. However, the additional re-time stage increases the power consumption and latency.
For example, in one conventional CDR scheme that uses a delay/phase locked loop to recover clock and data, multi-phase clocks are generated from a delay chain and used in a multiplexer/interpolator to generate a clock signal for a retimer, which generates a data output from a data input. A phase detector/controller is used to control the multiplexer/interpolator based on the data output. In such a scheme, there is a trade-off between jitter tolerance and jitter transfer. For example, if the bandwidth of the CDR loop is low, the jitter tolerance suffers; if the bandwidth of the CDR loop is high, the performance in jitter transfer suffers.
Another conventional scheme is based on the above discussed conventional CDR scheme. A so called clean-up PLL takes the clock signal generated multiplexer/interpolator to generate a cleaner clock for a further retimer, which takes the output of the previous retimer to generate the data output. The clean-up PLL can have a smaller bandwidth than that of the CDR loop in front of it and thus generate output data with less jitter. In such a scheme, a first stage retimer with a high loop bandwidth is used for improved jitter tolerance; and a second stage with a low loop bandwidth is used to improve the performance in jitter transfer. Such a scheme has been used in repeaters of data communication systems. Disadvantages of such a scheme include higher power consumption and higher latency.
Still another conventional scheme, often used in applications where the local clock has the same or similar frequency as that of the input data, makes use of a First-In-First-Out (FIFO) buffer to align phase and frequency of the input data with that of the local clock. Such a scheme increases the latency of the data from input to output; and systems using such a scheme may need to be re-calibrated when the input data stream has a varying delay relative to the local master clock. See, for example, Min Xu, Saied Benyamin, Xiaomin Si, et al, “An SFI-5 Compliant 16:4 Multiplexer for OC-768 Systems”, ISSCC 2003/SESSION 13/40 Gb/s COMMUNICATION ICS/PAPER 13. 5.